![]() I was expecting that everything went fine given that the CRC code doesn't do much if not creating connections. Signal crc_t : std_logic_vector (NBit-1 downto 0):= (others => '0') -registro temporaneo su cui fare le operazioniĬrc => crc_t(i), -funziona benissimo se metto dout(i) Signal output_LFSR :std_logic_vector(poly-1 downto 0) Ĭonstant crc_check :std_logic_vector(poly-1 downto 0):= (others => '0') Įlsif(t=poly-1 and output_LFSR(t)='0') then Signal input_temp :std_logic_vector(Nbit-1 downto 0) Input :in std_logic_vector(Nbit-1 downto 0) ĭout_s :out std_logic_vector(Nbit-1 downto 0) ĭout_r :out std_logic_vector(Nbit-poly-1 downto 0)ĭout :out std_logic_vector(N-1 downto 0) ![]() Md :in std_logic -1 per sender, 0 per receiver So the project is actually composed by the CRC box that contains the LFSR made by DFF. This is for a CRC encode and decode using a Linear Feedback Shift Register that uses D-FlipFlop as components. While all the code is perfectly compiled by ModelSim, I can't simulate it because of "Error loading design"
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